Multi core Commercial Off-the-Shelf (Cots) Under the implementation of fault Tolerance
The fault-tolerant design is applicable to high performance IT systems, increased by an amount of false contacts from smaller structures. As a substitute for the hardware solutions that are based on software error tolerance mechanisms, proper solution can increase the reliability for the commercial-of-the-shelf (COTS) multicore processors within a cheaper range with efficiency for further use. This paper aims to create a hybrid approach to hardware-related software, the current Core Intel x86 family and Xeon multi-core platforms. To support memory transactional hardware (TSX Intel) in creating implicit hits and fast rollback redundant process execution and signature comparison for error detection and error recovery can be done through transactional packing. Existing applications have improved redundant instrumentation performance with tolerance to post-binary compound errors. Further physical improvement increases the applicability of the CPU SPEC benchmark approach proposed in 2006 with administrative costs and rated performance over 47% on average based on the existence of proposed hardware support. In this paper, all the techniques for hardware and software level that help us for the removal of faults in multi-core commercial-of-the-shelf (COTS) and that makes the system able enough to work properly.